Computer History — Specific Machines  

Phase 1

Phase 2

Phase 3

CDC 1604
1958
Seymour Cray
first all-transistor computer

IBM 7030 Stretch
1961
300 KFLOPs

Phase 4

CDC 6600
1964
Seymour Cray
100 ns cycle time, 1 MFLOPs
60-bit words, parallel processing, RISC-like design

CDC 7600
1969
Seymour Cray
27.5 ns cycle time, 10 MFLOPs (36 MFLOPs peak)

Cray-1
1976
Seymour Cray
12.5 ns cycle time, 136 MFLOPs (250 MFLOPs peak)

SGI R10000
1996?
SPECint95: 11.4 SPECfp95: 19.1

Cray X-MP
1983
9.5 ns cycle time, 2 CPUs, 400 MFLOPs

Phase 5

Cray-2
1985
1-2 GFLOPS

ETA Systems ETA-10G
early 1987
7 ns cycle time, 10 GFLOPs

Cray-3
1989
4-5 GFLOPS
1 GHz GaAs processors

Cray-4
1995
smaller than the human brain

One of the "Seymour Stories" related in the wake of Seymour Cray's death was told by Larry Smarr, Director of the National Center for Supercomputing Applications at the University of Illinois at Urbana-Champaign:

When Seymour left Cray Research to form Cray Computer in the early 1990's, I was the fifth visitor he invited to Colorado Springs to review his plans for the Cray 3. He had a private lunch with me, one I will remember all my life. I asked him at one point what the next qualitative step for supercomputing would be. He paused and thought for a moment, then said, "I think it will be biological computing--using DNA and proteins as the computing elements just as Nature does." This was before the first tentative steps in that direction were announced by frontier researchers in this yet-to-be-born field. I asked him if he thought that he would be involved in building such machines and he said matter-of-factly, "no, I don't think I will live to see that day..."

Phase 6

ASCI project: ASCI stands for Accelerated Strategic Computing Initiative, and is a US DOE-DP (Department of Energy, Defense Programs office) program created in 1995 and (as currently planned) involving $1 billion over ten years (from 1995 to 2004). Under this program a 1.3 TFLOP machine was created by the end of 1996.

The ASCI program was created mainly to facilitate U.S. participation in the Comprehensive Nuclear Test Ban treaty, by allowing us to simulate a nuclear weapon test entirely on the computer. The program is roughly evenly divided between the three DOE-DP laboratories (Los Alamos, Lawrence Livermore, and Sandia) which have historically had a major role in nuclear weapons research as well as other big scientific computing projects. Each of the three laboratories is involved in a different supercomputer system project, and each has a different commercial contractor:

Laboratory Contractor ASCI Project name Architecture
Sandia Intel Option Red based on Intel Paragon, with Pentium-Pro nodes
Los Alamos SGI (Cray division) Option Blue Mountain linked Origin 2000 systems (MIPS R10000 nodes)
Lawrence Livermore IBM Option Blue Pacific based on POWER Parallel, POWER2 nodes

The remaining two current projects (the option Blue systems) should be complete by the end of 1998 or early 1999 and run at 3 TFLOPS each.

Another ASCI project (called PathForward) is working on developing the technology for faster machines. It focuses on developing those parts of the system which cannot be built from mass-market parts (mainly interconnect speed, debugging techniques and archival mass storage capacity). The schedule calls for 10 TFLOPS by the end of 1999, 30 TFLOPS by 2001 and 100 TFLOPS by 2004. Note that these might be accomplished by linking two or more machines together, if the interconnect bandwidth is high enough (the initial Blue Mountain system works that way, for example). Throughout the program the systems developed will have approximately the following performance characteristics (expressed as ratios): 1 TFLOPS performance / 16 TB/sec cache bandwidth / 3 TB/sec memory bandwidth / 1 TB memory / 100 GB/sec I/O bandwidth / 10 GB/sec disk bandwidth / 50 TB hard disk / 1 GB/sec archival storage bandwidth / 10 PB archival storage. Description of PathForward, with first reference to the word 'PetaFLOPS'

ASCI Option Blue Pacific (initial)
199604 (delivered)
IBM
256 processors (66 MHz POWER2)

SGI Origin 2000
199610 (introduced)
Cray Research division of Silicon Graphics
(successor to the Challenge and POWER CHALLENGE architecture)
up to 128 processors (R10000)
2 processors per node
nodes linked by hypercube network of parallel bus links
bisection bandwidth: 20 GB/sec for a 128-processor system

ASCI option Blue Mountain (initial)
199612 (delivered)
Cray Research division of Silicon Graphics
description: 7 SGI Origin 2000 systems with a total of 256 processors (R10000) and 32 GB RAM
linked by 800-MB/sec HIPPI links through four 16-way crossbars

ASCI Option Red (partial)
199612 (partial system)
Intel
(successor to the Paragon architecture)
7264 processors (200 MHz Pentium Pro)
2 processors per node

ASCI Option Red (at Sandia)
199706 (operational)
Intel
(successor to the Paragon architecture)
US $55 million, "peak" speed 1.8 TFLOPS
9072 processors (200 MHz Pentium Pro)
288 GB memory
2 processors per node
nodes linked by 38 x 32 x 2 mesh, 800 MB/sec over each link
bisection bandwidth is 60.8 GB/sec (cutting horizontally), or 51.2 GB/sec (cutting vertically)

ASCI option Blue Mountain (at Los Alamos)
199812 (projected delivery)
Cray Research division of Silicon Graphics
3072 processors (R10000)

ASCI Option Blue Pacific (at Lawrence Livermore)
199812 (projected delivery)
IBM
US $96 million, "peak" speed 3.2 TFLOPS
4096 processors (66 MHz POWER2)


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[http://www.astro.umd.edu/~nemo/peta/summers2.html]. 11 December 1995.

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